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Although there are quirks and pet peeves, any electrical engineer wants the printed circuit to match his schematic. Any perfect duplicate of his intentions will include this. For this reason, the stable data for a printed circuit layout is the schematic. A stable datum is a datum along which all other data align. From any confusion, order and sanity can emerge providing one merely selects a datum, assigns it importance or seniority and then begins to align other data against it. The stable datum for printed circuit design is this: If it says it is such a way in the schematic, then that is the way it must be in the PCB layout. The schematic contains the stable data with which the printed circuit layout data must align. Sometimes I have heard it said this way: "The schematic is the Bible." The primary alignment of data that has to occur here is electrical. If the schematic says connect pin 11 of U2 to pin 1 of U1, then the PCB layout had better provide for a copper trace that
There is an additional mechanical aspect in the alignment of PCB layout data to the stable data of the schematic. If the footprint as laid out for U2 is wrong, it will not accept the actual part for soldering, so there is no direct way for its pin 11 to get to U1 pin 1. This aspect requires a bit more information than just the schematic. The schematic says U2 is say, a quad nor-gate. It may also specify which footprint the device is packaged into, such as a 14-pin DIP . Often such information is not visible, but buried within the schematic database. So the PCB designer will need that additional information from the electrical engineer, who could extract it as part of a BOM and supply mechanical information as well by means of a specifications sheet, or "spec sheet." These two areas of duplication of the schematic are always what an electrical engineer wants. He wants all the parts he buys to fit on the board, and he wants the connections to match his schematic. Anything else he wants, he'll either expect you to know as part of the basics of PCB design or he'll tell you. If he doesn't get these two things from the PCB designer, then he can't examine his own circuit design in practice until he makes the prototype PCB match his own schematic by means of cuts and jumpers. But he shouldn't have to do such rework; the PCB designer should have done his job right in the first place. The more insidious error is one of connectivity. A part that doesn't fit is an obvious error. Now suppose that everything looks fine, but one or more connections go to different places than the schematic says they should. If the engineer doesn't do a line-by-line check of the layout, then the errors enter into the prototype board, which doesn't function as expected. Then the engineer has to find out that the PCB design didn't match his schematic and fix that with cuts and jumpers until it does. Only then can he debug his own design flaws. Most engineers aren't going to be happy about doing this, although some are quite gracious and are used to it. For "Streamlined PCB Design" to mean anything at all, it would have to guarantee that the connectivity of the PCB exactly matches, or "perfectly duplicates" that of the schematic. And then we come to one final thing that a "double-E" wants from a PCB designer, and that is not to be robotic about the PCB matching the schematic. If the PCB designer notices something unusual or ambiguous about the schematic, he should talk to the engineer about it. An engineer will certainly appreciate any of his own errors or omissions being caught before the prototype is built. A common example of a schematic error is omitted bypass caps on simple logic devices. This can occur because the default logic symbols for the parts don't include the power and ground connections at the corner pins (for example pins 7 for ground and pin 14 for power in a 14-pin device), so the bypass caps can get overlooked. Most engineers will want the PCB designer to point out the omission and ask if he wants to add the bypass caps. They coordinate on reference designators , the engineer updates his schematic, and the PCB design remains true to the concept that the schematic represents the stable data. Now there is one additional caveat to all this. When I say the electrical engineer wants the printed circuit to match his schematic, I'm talking about the hard copy of the schematic. Unfortunately, the schematic computer files may be quite different internally from the hard copy. That is why we always, always, always check the netlist extracted from the schematic database against the hard copy. In our experience, we have found quite a diversity of disagreement between the two. Some engineers have mastered the schematic software they use and applied their own personal version of "Streamlined Design" to really make the schematic follow the policy: "The schematic is the 'bible'." We rarely, extremely rarely, find nothing to correct from our netlist check. As Rosanne Rosanna-Dana used to say, "There's always somethin'." Here is an example: Usually there are at least transistor pin-outs to correct. Many engineers use a handful of generic logic symbols (in their schematics) for the myriad of possible transistor devices. This is fine for them, but the PCB designer then has to really nail down the pin-outs by examining spec sheets. Also, some transistor packages have a group of pins connected to the same net , but the schematic may show this as only one pin. If the electrical engineer is lucky enough to have you as a PCB designer doing his final schematic cleanup (even better, all of the CAD portion of the design), then here is where you can get Streamlined Design into full swing and create a schematic that is the "bible" for real . Once the details of proper pin-outs, PCB footprints and the nuances of a schematic designed with "Steamlined Design" are all in place, then everything downstream from the schematic is set up to also be streamlined: Fast, accurate and cost-effective. Get a quote: : sales Related topic: Electronic project revisions and streamlined schematics. © 2001-2005 John W. Childers. All Rights Reserved. Revised Thursday, January 31, 2008 |
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